Echelon FTXL Hardware User Manual

FTXL Hardware Guide078-0364-01A®

2 FTXL Hardware Overview Overview Echelon’s Free Topology Smart Transceivers provide a well-tested and cost-effective

FTXL Hardware Guide 3 The FTXL Developer’s Kit The FTXL Developer’s Kit is a development toolkit that contains the hardware designs, software

4 FTXL Hardware Overview • RAM, read/write non-volatile memory (such as flash) to store configuration data, and non-

FTXL Hardware Guide 5 • External memory (such as external RAM) for the FTXL application program • Non-volatile memory (such as flash memory

6 FTXL Hardware Overview and functions with the LonTalk Compact API, so that it is possible to migrate a ShortStack™

FTXL Hardware Guide 7 2 FTXL Developer’s Kit Hardware This chapter describes the three development boards that comprise the hardware for the

8 FTXL Developer’s Kit Hardware Overview of the FTXL Developer’s Kit Hardware The FTXL Developer’s Kit requires the t

FTXL Hardware Guide 9 Table 3. Hardware Development Platform for the Nios II Processor devboards DBC2C20 Altera Cyclone II Development Board

10 FTXL Developer’s Kit Hardware Figure 1. Service Pin Button and LED on the DBC2C20 Development Board Table 4. FTXL

FTXL Hardware Guide 11 Jumper Settings The DBC2C20 development board includes three sets of jumpers (P10, P19, and P21). For the FTXL Develop

Echelon, LONWORKS, LONMARK, LonTalk, Neuron, 3120, 3150, and the Echelon logo are trademarks of Echelon Corporation registered in the United States an

12 FTXL Developer’s Kit Hardware FTXL Function DBC2C20 Function DBC2C20 Name Main power Power supply connector P11

FTXL Hardware Guide 13 The FTXL Adapter Board The primary function of the FTXL Adapter Board is to provide the 5 V power to the FTXL Transceiv

14 FTXL Developer’s Kit Hardware Table 7. FTXL Adapter Board Connectors and Headers FTXL Developer’s Kit Function F

FTXL Hardware Guide 15 L2MIP_IRQCTSHRDYRSTA0R/W-J1Hirose FX8C-120P-SV2135791113151719212325272931333537394143454749515355575961636567697173757

16 FTXL Developer’s Kit Hardware LEDs The FTXL Transceiver Board includes two LEDs (D11 and D14). These LEDs are act

FTXL Hardware Guide 17 Figure 5 shows the connections for the J3 and J4 Hirose stacking headers; Figure 6 on page 18 shows the connections for

18 FTXL Developer’s Kit Hardware J2Hirose FX8C-120S-SV513579111315171921232527293133353739414345474951535557596163656

FTXL Hardware Guide 19 3 FTXL Transceiver Hardware Interface This chapter describes the hardware interface for the FTXL Transceiver Chip, whi

20 FTXL Transceiver Hardware Interface Overview of the Hardware Interface The hardware interface for an FTXL Transce

FTXL Hardware Guide 21 Pull-Up Resistors for Communications Lines For the parallel communications interface, you must add 10 kΩ pull-up resist

FTXL Hardware Guide iii Welcome Echelon’s FTXL™ products enable any product that contains an Altera® Nios® II processor to quickly and inexpen

22 FTXL Transceiver Hardware Interface FTXL Transceiver Pin Number FTXL Transceiver Pin Name Signal Name Direction

FTXL Hardware Guide 23 Figure 7. The FTXL Transceiver Parallel Interface From the point of view of the host processor, the FTXL Transceiver a

24 FTXL Transceiver Hardware Interface The FTXL LonTalk protocol stack and the FTXL Transceiver pass the write token

FTXL Hardware Guide 25 Transceiver, this pin is not part of the communications port, and does not function as a sleep control pin, but acts as

26 FTXL Transceiver Hardware Interface • Program recovery If an application experiences unexpected behavior becaus

FTXL Hardware Guide 27 Software Controlled Reset When the CPU watchdog timer expires, or a software command to reset occurs, the RESET~ pin is

28 FTXL Transceiver Hardware Interface When an externally generated clock is used to drive the CLK1 CMOS input pin o

FTXL Hardware Guide 29 FPGA Design Pin Name FPGA Pin Number Direction Edge Capture Corresponding FTXL Transceiver Pin FTXL_RESET G16 Bidirecti

30 FTXL Transceiver Hardware Interface and A0, and waits for the assertion of D0/HS, and then deasserts A0, asserts

FTXL Hardware Guide 31 Figure 10. Timing Diagram for Reading the Length Byte Figure 11 shows a detailed timing diagram for reading the data.

iv Networking Protocol, and provides a high-level introduction to LONWORKS networks and the tools and components that are used for developing, install

32 FTXL Transceiver Hardware Interface Control Flow: Host Sending Data to the FTXL Transceiver When the host progra

FTXL Hardware Guide 33 Read HandshakeHandshake (D0) readyA0 high -> D0 is handshakeR/W~ low -> readWrite length = 0x13R/W~high -> wr

34 FTXL Transceiver Hardware Interface Read Handshake(Ready)Write Data (0x12)Read Handshake (Busy)Read Handshake (Re

FTXL Hardware Guide 35 D=0x00D=0x30D=0x80D=0x00D=0x7FD=0xD1D=0x04D=0xCDD=0xD3D=0x01D=0x9FD=0x00D=0xFFD=0xFFD=0x06D=0x0AD=0x00D=0x04D=0x11D=0x0

FTXL Hardware Guide 37 4 FPGA Design for the FTXL Transceiver This chapter describes FPGA design considerations for an FTXL device.

38 FPGA Design for the FTXL Transceiver Overview The hardware for an FTXL device consists primarily of an FTXL Trans

FTXL Hardware Guide 39 To develop a new FPGA design, you must use the Altera Quartus II software, version 7.2 or later (either the Web Edition

40 FPGA Design for the FTXL Transceiver multipliers, embedded memory blocks, phase-locked loops (PLLs), and high-spe

FTXL Hardware Guide 41 Figure 17. Quartus II Device and Pin Options Dialog See the Altera Configuration Handbook for more information about F

FTXL Hardware Guide v Product Category Documentation Titles Cyclone® II and Cyclone III FPGA and device configuration Cyclone II Device Handb

42 FPGA Design for the FTXL Transceiver Component Name Class Name File Names Description FTXL Parallel I/O Transce

FTXL Hardware Guide 43 • The A0 signal is delayed by two clock cycles. • The R/W~ signal is delayed by one clock cycle. Figure 19 shows th

44 FPGA Design for the FTXL Transceiver Figure 20. Quartus II Component Editor Dialog for FTXL Parallel I/O Signals

FTXL Hardware Guide 45 Figure 21. Quartus II Component Editor Dialog for FTXL Parallel I/O Interfaces (Part 1)

46 FPGA Design for the FTXL Transceiver Figure 22. Quartus II Component Editor Dialog for FTXL Parallel I/O Interfa

FTXL Hardware Guide 47 • chipselect: Select signal to enable access to the LED • write_n: Write-select signal to write to the LED • write

48 FPGA Design for the FTXL Transceiver • chipselect: Select signal to enable access to the reset pin • write_n:

FTXL Hardware Guide 49 • 8 MB CFI flash memory • 16 MB SDRAM These numbers correspond to the external memory provided by the DBC2C20 develop

50 FPGA Design for the FTXL Transceiver Component Component Name Size (Bytes) SDRAM interface for the DBC2C20 devel

FTXL Hardware Guide 51 Within the FTXL software, the FTXL HAL is defined in two files: FtxlHal.h and FtxlHal.c. Other Hardware Design Conside

vi

FTXL Hardware Guide 53 5 Working with the Altera Development Environments This chapter describes how to use the Altera Complete Design Sui

54 Working with the Altera Development Environments Development Tools To develop your FTXL application, you use ver

FTXL Hardware Guide 55 Using a Device Programmer for the FPGA Device To load your hardware design, software application, and the FTXL LonTalk

56 Working with the Altera Development Environments Setting Component Search Paths To work with an FPGA design that

FTXL Hardware Guide 57 To add FTXL components to the SOPC Builder library path: 1. Start the Quartus II software. 2. Open a Quartus II proje

58 Working with the Altera Development Environments a. Expand the Bridges and Adapters folder. b. Expand the Memor

FTXL Hardware Guide 59 e. If necessary, modify the assigned IRQ number for the component; see Addressing, Size, and IRQ Requirements on page

60 Working with the Altera Development Environments Modifying the Quartus II Design Before you begin, ensure that th

FTXL Hardware Guide 61 Figure 26. Connections for FTXL_PIO_Delay Component Finally, you need to add pins to the symbol blocks for the FTXL co

FTXL Hardware Guide vii Table of Contents Welcome...

62 Working with the Altera Development Environments 6. Load the modified hardware design for the Nios II processor

FTXL Hardware Guide 63 A Using the Bring-Up Application to Verify FTXL Hardware Design This chapter describes how to use the Bring-Up appli

64 Using the Bring-Up Application to Verify FTXL Hardware Design Overview This appendix describes the Bring-Up appl

FTXL Hardware Guide 65 The FtxlHal.c file defines the following functions to handle interrupts: • LonRegisterIsr() Initializes the interrupt

66 Using the Bring-Up Application to Verify FTXL Hardware Design LonDeassertTransceiverReset() functions write to th

FTXL Hardware Guide 67 Signal Name FTXL Transceiver Pin Action D2 2 D3 43 D4 42 D5 36 D6 35 D7 32 When LonReadTransceiverDataRegister() read

68 Using the Bring-Up Application to Verify FTXL Hardware Design To write each byte, the application must first wait

FTXL Hardware Guide 69 The application uses the functions described in Interrupt Functions from the FTXL HAL on page 64 to handle interrupts.

70 Using the Bring-Up Application to Verify FTXL Hardware Design Building the Application Image To build the softwar

FTXL Hardware Guide 71 The output of each test lists the test name together with an indication of whether it passed or failed. For some of th

viii FPGA Design for the FTXL Transceiver... 37 Overview ...

72 Using the Bring-Up Application to Verify FTXL Hardware Design Read Status (Busy)Host asserts resetHost deasserts

FTXL Hardware Guide 73 Read HandshakeHandshake (D0) busyA0 high -> D0 is handshakeCS~ low -> transfer in progressRW~ high -> read

74 Using the Bring-Up Application to Verify FTXL Hardware Design Read HandshakeWrite length = 0Handshake (D0) busyHa

FTXL Hardware Guide 75 The figure also shows the status being read after the token is passed. Read Status (Ready)Write Length 0Read Status (Bu

76 Using the Bring-Up Application to Verify FTXL Hardware Design Read HandshakeRead length = 0Handshake (D0) busyHan

FTXL Hardware Guide 77 Figure 33 shows the signals while writing the downlink data. Read Status (Ready)Write Length (9)Read Status (Busy)Read

78 Using the Bring-Up Application to Verify FTXL Hardware Design Figure 34. Reading the Uplink Data Interrupt Test

FTXL Hardware Guide 79 • outputDataStream – To write a frame to the host, the frame is first copied to this buffer (including the length byte

80 Using the Bring-Up Application to Verify FTXL Hardware Design Designing Additional Tests The tests described in R

FTXL Hardware Guide 81 Index A A0 pin, 22 addressing requirements, 49 Altera Complete Design Suite, 54 application image building, 61 loading,

FTXL Hardware Guide 1 1 FTXL Hardware Overview This chapter provides an overview of the FTXL Developer’s Kit and the development process for

82 Index headers, 16 jumpers, 16 LEDs, 16 overview, 15 H HAL, 50 handshaking, 23 hardware abstraction layer, 50 hard

FTXL Hardware Guide 83 signals. See pins software-controlled reset, 27 SOPC Builder, 54 status signals, bring-up application, 66 T test data p

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