Echelon Neuron User Manual Page 210
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Mnemonic Operand Operation Description
NOP IP = IP + 1 No operation is done.
NOT TOS = NOT TOS
C = 0
IP = IP+1
Change TOS to its one's
complement.
OR
TOS = TOS OR [DSP--]
C = 0
IP = IP+1
Bitwise OR of TOS and NEXT.
Drop NEXT.
OR #literal TOS = TOS | LITERAL
C = 0
IP = IP+2
OR literal with TOS.
OR_R TOS = TOS OR [DSP--]
C = 0
Return
Bitwise OR of TOS and NEXT.
Drop NEXT. Return to caller.
POP absolute
address
[absolute address] = TOS
TOS = [DSP--]
IP = IP+3
Pops TOS and stores it at the
absolute address.
POP !D [BP+D] = TOS
TOS = [DSP--]
IP = IP+1
Pops TOS and stores it at the
BP plus displacement address
D.
Displacement range is 8..23.
POP !TOS [BP+TOS] = [DSP--]
IP = IP+1
Pops next element and stores it
at the BP plus TOS address.
TOS unchanged.
POP [PTR] [D] [[BP+(PTR*2)]+D] = TOS
TOS = [DSP--]
IP = IP+2
Pops TOS and stores it at the
address held in 2-byte pointer
PTR plus unsigned
displacement D of 0 to 255.
POP [PTR] [TOS] [[BP+(PTR*2)]+TOS]=[DSP--]
IP = IP+1
Pops next element and stores it
at the address held in 2-byte
pointer PTR plus TOS address.
POP CPUREG CPUREG = TOS
TOS = [DSP--]
IP = IP+1
Pops TOS and stores it in the
specified register.
CPUREG = FLAGS, RSP, DSP
200 Neuron Assembly Instructions Listed by Mnemonic
- Neuron Assembly 1
- Language Reference 1
- Welcome 3
- Audience 3
- Related Documentation 3
- Table of Contents 5
- Introduction 11
- Neuron Assembler Tools 13
- Command Usage 14
- NAS Command Switches 14
- Neuron Librarian Tool 15
- Assembler Files 16
- Source Files 16
- Naming Convention 16
- File Format 17
- Output Files 17
- Assembly Instructions 19
- Operands 20
- Literal Constants 20
- Symbols 21
- Expressions 21
- Constant Expressions 23
- Comments 24
- Assembler Directives 24
- Assembly Programming 25
- Neuron Architecture 26
- CPU Registers 27
- General-Purpose Registers 28
- Pointer Registers 29
- Flag Register 31
- Instruction Pointer 31
- Data Stack 32
- Return Stack 33
- Stack Manipulation 34
- Segments 35
- Using Neuron Chip Memory 36
- Chips with Off-Chip Memory 36
- Chips with Auto-tuned Memory 39
- Addressing Modes 40
- Immediate 40
- Absolute 40
- Implicit 41
- Pointer Direct 41
- Indirect Relative 41
- Indirect Indexed 42
- DSP Relative 42
- BP Relative 43
- BP Indexed 43
- Indirect 43
- Relative 43
- Function 45
- Stack-Effect Comments 51
- Multi-Byte Values 51
- Pointer Values 51
- Conditional Values 51
- Showing the Return Stack 52
- Integrating the Program 52
- Assembling the Program 53
- Linking the Program 54
- Debugging the Program 54
- Interfacing with a Neuron C 57
- Application 57
- Overview 58
- Naming Conventions 58
- Function Parameters 58
- Calling Conventions 59
- Data Representation 61
- Structures and Unions 62
- Bitfields 62
- Neuron Assembly Language 69
- Instruction Statements 69
- ADC (Add with Carry) 74
- ADD (Add) 75
- ADD_R (Add and Return) 76
- ALLOC (Allocate) 77
- AND (And) 78
- AND_R (And and Return) 79
- BR (Branch) 80
- BRC (Branch If Carry) 81
- BRF (Branch Far) 82
- BRNC (Branch If Not Carry) 83
- BRNEQ (Branch If Not Equal) 84
- BRNZ (Branch If Not Zero) 86
- BRZ (Branch If Zero) 87
- CALL (Call Near) 88
- CALLF (Call Far) 89
- CALLR (Call Relative) 90
- DEC (Decrement) 94
- DIV (Divide) 95
- DROP (Drop from Stack) 96
- INC (Increment) 98
- Done 99
- MUL (Multiply) 100
- NOP (No Operation) 101
- NOT (Not) 102
- OR (Or) 103
- OR_R (Or and Return) 104
- POP (Pop from Stack) 105
- ] DA 2 7 None 106
- ] D9 2 7 None 106
- ] DB 2 7 None 107
- POPD (Pop Pointer Direct) 110
- Return Stack) 111
- PUSH (Push onto Stack) 112
- PUSH [1][offset] 113
- 98 2 7 None 114
- ] 99 2 7 None 114
- ] 9A 2 7 None 114
- ] 9B 2 7 None 114
- PUSHD (Push Pointer Direct) 117
- Data Stack) 119
- PUSHS (Push Short) 120
- RET (Return from Call) 121
- SBC (Subtract with Carry) 124
- SBR (Short Branch) 125
- SBRZ (Short Branch If Zero) 129
- SHL (Shift Left) 131
- SHR (Shift Right) 133
- SUB (Subtract) 135
- XCH (Exchange) 137
- XOR (Exclusive Or) 138
- Neuron Assembler Directives 141
- ELSE (Conditional Assembly) 147
- END (Assembly Control) 148
- ENDIF (Conditional Assembly) 149
- EQU (Equate Symbol) 150
- ERROR (Conditional Assembly) 151
- EXPORT (Export Symbol) 152
- IF (Conditional Assembly) 153
- IFDEF (Conditional Assembly) 154
- INCLUDE (Assembly Control) 157
- LIBRARY (Include Library) 158
- LIST (Listing Control) 160
- NOLIST (Listing Control) 161
- ORG (Segment Control) 162
- PAGE (Listing Control) 163
- RADIX (Default Radix) 164
- RESOURCE (Resource Control) 166
- SEG (Segment Control) 167
- SUBHEAD (Listing Control) 168
- System-Provided Functions 169
- Overview of the Functions 170
- _add16 (Add, 16 Bit) 171
- _add16s (Add Signed, 16 Bit) 171
- -- value(2)+offset) 172
- _and16 (And, 16 Bit) 173
- _dec16 (Decrement, 16 Bit) 173
- _div16 (Divide, 16 Bit) 174
- _div8 (Divide, 8 Bit) 175
- _get_sp (Get Stack Pointer) 179
- _inc16 (Increment, 16 Bit) 179
- _less16 (Less Than, 16 Bit) 184
- _less8 (Less Than, 8 Bit) 184
- _log8 (Logical Value, 8 Bit) 185
- Bits to 16 Bits) 187
- Converts 8 Bits to 16 Bits) 187
- _max8 (Maximum Value, 8 Bit) 189
- _memcpy (Copy Memory) 190
- _memset (Set Memory) 190
- _memset1 (Set Memory at P0) 191
- _min8 (minimum Value, 8 Bit) 192
- _mod8 (Modulo, 8 Bit) 193
- _mul16 (Multiply, 16 Bit) 193
- _mul8 (Multiply, 8 Bit) 194
- _not16 (Not, 16 Bit) 196
- _or16 (Or, 16 Bit) 197
- 16 Bit) 198
- Offset, 16 Bit) 198
- -- value, …, value, …) 199
- NEXT, 16 Bit) 200
- _sub16 (Subtract, 16 Bit) 203
- Neuron Assembly Instructions 205
- Listed by Mnemonic 205
- Instructions by Mnemonic 206
- Listed by Hexadecimal Opcode 217
- Instructions by Opcode 218
- 1 2 7 224
- Reserved Keywords 229
- Keywords 230
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